The present invention relates to a digital-to-analog or DA converter of the type which delivers a DC output by switching a reference voltage in response to a pulse whose duration in turn is varied in response to a digital input.
In FIG. 1 there is shown a prior art DA converter which delivers a DC output in response to a digital signal comprising of four bits. It has four T flip-flops 2a-2d connected in cascade and clock pulses at a clock pulse input terminal 1 are applied to a T terminal of the first-stage flip-flop 2a. Outputs A, B C and D of these flip-flops 2a-2d are applied to a NOR gate 3 whose output is applied through an inverter 4 to an input terminal S of a RS flip-flop 5. Outputs A, B, C and D are applied to one inputs of AND gates 6a-6d and a binary coded signal is applied to four input terminals 7a-7d. For instance, bits of input signals (1,0,0,0), (0,0,0,0) and so on are applied to the input terminals 7a-7d, respectively. These input terminals are connected through inverters 8a-8d to the other inputs of AND gates 6a-6d and directly to one inputs of AND gates 9 a-9d whose the other inputs are applied with outputs A, B, C and D of the flip-flops 2a-2d. The outputs of the AND gates 6a-6d and 9a-9d are so wired as to provide an OR output which in turn is applied through an inverter 11 to an input R of the flip-flop 5 whose output Q is applied through a resistor 12 to a base of a switching transistor 13 with a collector impressed with a DC voltage E from a terminal 15 through a resistor 14. The collector output from the transistor 13 is smoothed by a filter 16 and a DC voltage is derived from an output terminal 17.
Next referring further to FIG. 2, the mode of operation of the DA converter with the above construction will be described. A clock pulse train shown in FIG. 20 is applied to the input terminal 1 so that the flip-flops 2a-2d deliver the outputs as shown in FIGS. 2 A, A, B, B, C, C, D and D. Assume that an input signal (1,0,0,0) is applied to the input terminals 7a-7d. Then, the A output of the first flip-flop 2a is (1), the AND gate 9a delivers the output (1), and when the B, C and D outputs of the flip-flops 2b, 2c and 2d are (1), the AND gates 6b, 6c and 6d deliver the outputs (1). Except for the above conditions, no (1) signal appears at a terminal 10, the output at this terminal being indicated at P.sub.1 in FIG. 2.
When another input signal (0,1,0,0) is applied to the input terminals 7a-7d, the AND gates 6a, 6c and 6d deliver the outputs (1) when the A output of the flip-flop 2a, the C output of the flip-flop 2c and the D output of the flip-flop 2d are (1). Alternatively, when the B output of the flip-flop 2b is (1), the AND gate 9b delivers the output (1). Except the above conditions, no (1) output appears at the terminal 10, the output at this terminal being indicated at P.sub.2 in FIG. 2.
When an input signal (1,1,1,1) is applied to the terminals 7a-7d, the AND gates 9a-9d deliver the outputs (1) when the A, B, C and D outputs from the flip-flops 2a-2d are (1). Except the above condition, no output (1) appears at the terminal 10, the output at this terminal being indicated at P.sub.16 in FIG. 2.
The A, B, C and D outputs of the flip-flops 2a-2d are applied to NOR gate 3 and when they are all (0), the NOR gate 3 delivers the output (1) which is inverted by the inverter 4 and applied to the S terminal of the RS flip-flop 5 as shown at S in FIG. 2. Therefore, when the output at the terminal 10 is P.sub.1, P.sub.2 or P.sub.16, the RS flip-flop 5 delivers the Q output as shown at Q.sub.1, Q.sub.2 or Q.sub.16 in FIG. 2. Thus, it is seen that in response to the binary coded input signal applied to the input terminals the pulse duration of the Q output of the RS flip-flop 5 varies. This Q output with a varying pulse duration is applied to the base of the switching transistor 13 to drive it into state (1) and the output of the switching transistor 13 is smoothed by the filter 16 to derive the DC voltage corresponding to the input signal.
The DA converter of the type described has a defect that the greater the number of bits of an input signal the higher the clock pulse frequency becomes. For instance, with a 14-bit DA converter with the switching frequency of the output of the RS flip-flop 5 being about 61 Hz, the clock pulse frequency is about 1 MHz. With the conventional P-channel MOS LSIs, the upper limit is about 1 MHz at which the signals may be processed in correct waveforms. Furthermore, the prior art DA converter has a defect that a filter or smoothing circuit large in size must be provided in order to handle the signals of a low frequency so that a rise time as well as a fall time of voltage are increased. Therefore, a lower switching frequency limit is about 60 Hz in practice.
A 14-bit DA converter which is used in an electronic tuning device for a television receiver consists of 14 T flip-flops and one RS flip-flop. For this purpose, the number of T flip-flops in the DA converter shown in FIG. 1 may be increased to 14.